| ############################################################# (1)建立目标板目录# 其中lowlevel_init.S采用adsvix的文件,以开启turbo mode,并注释掉# 其中对pxavoltage.S文件中initPXAvolatage函数的调用。############################################################cd board/cp -arv lubbock xsbase270mv xsbase270/lubbock.c xsbase270/xsbase270.ccp adsvix/lowlevel_init.S xsbase270/vim xsbase270/lowlevel_init.S@setvoltage:@ mov r10, lr@ bl initPXAvoltage@ mov lr, r10############################################################# (2)建立目标板配置头文件############################################################cd $U-BOOT/include/configscp lubbock.h xsbase270.h############################################################# (3)修改Makefile#####################################################################在$U-BOOT/Makefile中添加:xsbase270_config: unconfig@$(MKCONFIG) $(@:_config=) arm pxa xsbase270#########在$U-BOOT/Makefile中修改CROSS_COMPILE:CROSS_COMPILE = arm-iwmmxt-linux-gnueabi-#########在$U-BOOT/board/xsbase270/Makefile中修改:#COBJS := lubbock.o flash.oCOBJS := xsbase270.o |
| ############################################################## (1) cpu/pxa/config.mk##############################################################armv5-->armv5te, modified by aaron wongPLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale ############################################################## (2) include/asm-arm/mach-types.h#############################################################/* added by aaron */#define MACH_TYPE_XSBASE270 1141 |
| export BUILD_DIR=~/u-boot_xsbase270/build/make xsbase270_configmake |
| /** High Level Configuration Options (easy to change)*/#define CONFIG_PXA27X 1 /*to keep PXA27x specific code*/#define CONFIG_XSBASE270 1#define BOARD_LATE_INIT 1#undef CONFIG_USE_IRQ /* we don"t need IRQ/FIQ stuff */....../** Size of malloc() pool*/#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)#define CFG_GBL_DATA_SIZE 128 /** Stack sizes* The stack sizes are set up in start.S using the settings below*/#define CONFIG_STACKSIZE (128*1024) /* regular stack */#ifdef CONFIG_USE_IRQ#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */#endif/** Miscellaneous configurable options*/#define CFG_CPUSPEED 0x207 /* cpu start-up frequency,91MHz *//** GPIO settings*/#define CFG_GPSR0_VAL 0x00003000 #define CFG_GPSR1_VAL 0x00000000#define CFG_GPSR2_VAL 0x00010000#define CFG_GPSR3_VAL 0x00020000 #define CFG_GPCR0_VAL 0x00000800....../** Clock settings*/#define CFG_CKEN 0x00400200#define CFG_CCCR 0x08000290 /* 520 MHz *//** Memory settings*/#define CFG_MSC0_VAL 0x7FF82BD0#define CFG_MSC1_VAL 0x7FF87FF8#define CFG_MSC2_VAL 0x7FF87FF8#define CFG_MDCNFG_VAL 0x00001AC9 #define CFG_MDREFR_VAL 0x0000001E #define CFG_MDMRS_VAL 0x00000000 ....../** PCMCIA and CF Interfaces*/#define CFG_MECR_VAL 0x00000001#define CFG_MCMEM0_VAL 0x00010504#define CFG_MCMEM1_VAL 0x00010504...... |
| /** Physical Memory Map*/#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM*/#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ #define CFG_DRAM_BASE 0xa0000000#define CFG_DRAM_SIZE 0x04000000 #define CFG_FLASH_BASE PHYS_FLASH_1//you can also add other IO address map here, such as a FPGA |
| /** Command line configuration.*/#include <config_cmd_default.h> #define CONFIG_CMD_PING |
| /** select serial console configuration*/#define CONFIG_FFUART 1 /* we use FFUART on XSBASE270 */#define CONFIG_BAUDRATE 115200 |
| /** BOOTP options*/#define CONFIG_BOOTP_BOOTFILESIZE#define CONFIG_BOOTP_BOOTPATH#define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTDELAY 3#define CONFIG_ETHADDR 08:00:3e:26:0a:5b#define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 192.168.0.21#define CONFIG_SERVERIP 192.168.0.250#define CONFIG_BOOTCOMMAND "bootm 80000" #define CONFIG_BOOTARGS "root=/dev/ram0,rw mem=64M console=ttyS0, 115200"#define CONFIG_CMDLINE_TAG#define CONFIG_TIMESTAMP/* allow to overwrite serial and ethaddr */#define CONFIG_ENV_OVERWRITE |
| /** Hardware drivers*/#define CONFIG_DRIVER_SMC91111#define CONFIG_SMC91111_BASE 0x0C000000 #define CONFIG_SMC_USE_32_BIT 1 |
| /* file : include/flash.h */#define INTEL_ID_28F128K18 0x88068806 /* added by aaron */#define FLASH_28F128K18 0x00BA /*Intel 28F128K18 (128M=8Mx16)*/ |
| #define CFG_FLASH_CFI#define CFG_FLASH_CFI_DRIVER 1 /* avoid long time detection, added by aaron ,see include/flash.h */#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */#define CFG_MAX_FLASH_SECT 128 /*max number of sectors on one chip*/ /* timeout values are in ticks */#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /*Timeout for Flash Erase */#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /*Timeout for Flash Write */ /* write flash less slowly */#define CFG_FLASH_USE_BUFFER_WRITE 1 |
| /* NOTE: many default partitioning schemes assume the kernel starts at * the second sector, not an environment. You have been warned!*/#define CFG_MONITOR_BASE 0 #define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE#define CFG_ENV_IS_IN_FLASH 1#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE#define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)/* If defined, hardware flash sectors protection is used instead of * U-Boot software protection. */#define CFG_FLASH_PROTECTION |
| /** Miscellaneous configurable options*/#define CFG_HUSH_PARSER 1#define CFG_PROMPT_HUSH_PS2 "> "#define CFG_LONGHELP /* undef to save memory */#ifdef CFG_HUSH_PARSER#define CFG_PROMPT "$ " /* Monitor Command Prompt */#endif#define CFG_CBSIZE 256 /* Console I/O Buffer Size*//* Print Buffer Size */#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) #define CFG_MAXARGS 16 /* max number of command args */#define CFG_BARGSIZE CFG_CBSIZE /*Boot Argument Buffer Size*/#define CFG_DEVICE_NULLDEV 1 #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz *//*default load address */#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz *//* valid baudrates */#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| #include <common.h>DECLARE_GLOBAL_DATA_PTR;/* Miscelaneous platform dependent initialisations */ int board_init (void){/* memory and cpu-speed are setup before relocation *//* so we do _nothing_ here *//* arch number of XSBASE270-Board */ gd->bd->bi_arch_number = MACH_TYPE_XSBASE270; /* adress of boot parameters */gd->bd->bi_boot_params = 0xa0000100; return 0;} int board_late_init(void){setenv("stdout", "serial");setenv("stderr", "serial");return 0;} int dram_init (void){gd->bd->bi_dram[0].start = PHYS_SDRAM_1;gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;gd->bd->bi_dram[1].start = PHYS_SDRAM_2;gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;gd->bd->bi_dram[2].start = PHYS_SDRAM_3;gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;gd->bd->bi_dram[3].start = PHYS_SDRAM_4;gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; return 0;} |